Design and Analysis of RNS Based FIR Filter Using Verilog Language
نویسنده
چکیده
Digital filter plays an important role in Very Large Scale Integration (VLSI) technology. The existing Finite Impulse Response (FIR) filter has long transient response which is the major limitation. To overcome this drawback, Residue Number System (RNS) based FIR filters is developed which is described in this paper. High-speed is obtained by introducing the residue arithmetic concept that permits the computation of the filter output by using N FIR sub filters of reduced dynamic range operating in parallel form. Three moduli sets are used in RNS based Filter. 4tap Low Pass Filter (LPF) type of FIR filter and RNS based FIR filter with 4-tap LPF are designed using Verilog language and analyzed in this paper. The simulation is done by using Xilinx tool Integrated Software Environment (ISE)-13.1
منابع مشابه
FIR Filter Implementation Using Novel Modulo 2 n - 2 k - 1 Adder for RNS
A design of high performance modular adder with an application of FIR filter is implemented in this paper. Moduli set in the form of 2 n -2 k -1 (1≤k≤n-2) can offer excellent balance among RNS channels for multichannel RNS processing. Modular adder can be used in RNS addition, multiplication and division. In this paper, a Finite Impulse Response (FIR) filter using a novel algorithm and its Very...
متن کاملA Comparative Study on LUT and Accumulator Radix-4 Based Multichannel RNS FIR Filter Architectures
Abstract In this paper, a comparative study of two architectures proposed for multichannel reconfigurable FIR filter are performed in terms of complexity and speed. The proposed architectures, viz, dual port memory based LUT multiplier and accumulator based radix-4 multiplier architectures, are designed to reduce the complexity and to improve the speed of operation of multiplier used in multich...
متن کاملConstant-Coefficient FIR Filters Based on Residue Number System Arithmetic
In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set 1 {2 ,2 ,2 1} n n n + − , which avoids 2 1 n + modulus, is used to design...
متن کاملAn Efficient Constant Multiplier Architecture for Reconfigurable Fir Filter Synthesis
This paper proposes a reconfigurable finite impulse response (FIR) filter using constant multiplier algorithm with applying pipeline technique. To design a high performance Reconfigurable fir filter, according to the proposed constant multiplier algorithm with Retiming pipelining method has been applied in co-efficient generator block. This method capable of reducing the switching activity of c...
متن کاملOptimal fast digital error correction method of pipelined analog to digital converter with DLMS algorithm
In this paper, convergence rate of digital error correction algorithm in correction of capacitor mismatch error and finite and nonlinear gain of Op-Amp has increased significantly by the use of DLMS, an evolutionary search algorithm. To this end, a 16-bit pipelined analog to digital converter was modeled. The obtained digital model is a FIR filter with 16 adjustable weights. To adjust weights o...
متن کامل